Crypto Cores on FPGA

Cipher hardware, a broken stream cipher and power-trace side channels

Two lab sequences on a DE10-Standard: DES, Triple DES, RSA, AES and SHA-256 cores verified and run on the FPGA, a generated stream cipher put through NIST randomness testing and broken with a cube tester, and power traces captured on a ChipWhisperer.

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A Terasic DE10-Standard board lit up, its six seven-segment displays showing 0000FC — fig.01 · photograph

kind: project
course: ECE 4156 and ECE 3170, Georgia Tech
category: security
period: Jan 2025 - Dec 2025
status: completed

head -n 20 README

Cipher and hash cores brought up and verified on a Terasic DE10-Standard, a generated stream cipher that passed NIST randomness testing and then fell to a cube tester, and power traces captured from a live target on a ChipWhisperer-NANO.

The cores themselves were provided; my work was bringing them up on the board and verifying them, which meant testbenches and C reference models for every core, a six-state FSM wrapper that reuses one DES core for Triple DES at about 123 Mbit/s, a SHA-256 checker with a comparator against three known digests. I ran AES encrypt/decrypt on the DE10-Standard and checked board ciphertexts against C references (ModelSim + on-board vectors). A Python generator wrote the VHDL for a 170-bit composite Mersenne product register, I synthesized and compared six update polynomials, and 32 keystreams of 20,000 bits passed the NIST SP 800-22 suite. A cube tester that XORs the streams together then returned 20,000 zeros: the output was statistically random and structurally broken. For the side-channel labs I set up a ChipWhisperer-NANO, captured power traces of an STM32 target, located individual instructions in them, and recovered an AES key byte from a single leaked bit of S-box state in a simulated attack. The lectures alongside the labs covered PUFs, secure boot and hardware Trojans.

grep -n highlights

01Simulated, synthesized and ran DES, Triple DES, RSA, AES and SHA-256 cores on a DE10-Standard, validating each against a C reference model on 5x5 key and plaintext grids, encrypting then decrypting every block.
02Wrote the Triple DES wrapper: a six-state FSM that drives one DES core through encrypt-decrypt-encrypt at roughly 123 Mbit/s and 52 cycles per block at 100 MHz.
03Ran AES encrypt/decrypt on the DE10-Standard and checked board ciphertexts against C references (ModelSim + on-board vectors).
04Generated the VHDL for a 170-bit composite Mersenne product register from Python, synthesized six update polynomials, and measured 354 to 384 ALMs and 198 to 217 MHz on Cyclone V.
05Put 32 keystreams of 20,000 bits through the NIST SP 800-22 suite, then broke the cipher with a cube tester: the XOR of the streams was all zeros.
06Set up a ChipWhisperer-NANO with JupyterLab, captured power traces of an STM32 target, and recovered an AES key byte from one leaked S-box bit in a simulated attack.
07Studied PUFs, secure boot, hardware Trojans and semiconductor attack surfaces alongside the implementation work.

ls ./modules

01SHA-256 hash checkerProvided SHA-256 engine verified against six NIST vectors, wrapped with a comparator and a switch-driven state machine on the boardvhdl · modelsim · de10-standard

02AES-128 on the DE10-StandardRan AES encrypt/decrypt on the DE10-Standard and checked board ciphertexts against C references (ModelSim + on-board vectors)vhdl · c · modelsim

03DES, Triple DES and RSADES and RSA cores exercised on the board; the Triple DES FSM wrapper written from scratch with a full round-trip testbenchvhdl · c · quartus prime

04CMPR stream cipherPython-generated 170-bit product register inserted into a stream cipher, six polynomials compared, NIST tests passed, cube tester failedpython · vhdl · nist sts

05Power-trace side channelsChipWhisperer-NANO capture of an STM32 target and a simulated single-bit AES key recoverychipwhisperer · python · matplotlib

ls ./media

ModelSim waveform of the Triple DES wrapper stepping through three DES passes, producing a ciphertext and then recovering the plaintext — fig.02The Triple DES wrapper in simulation: three passes through one DES core, ciphertext out, plaintext back.

Terminal on the DE10-Standard showing an AES ciphertext word from the board run — fig.03AES encrypt/decrypt on the DE10-Standard, with board ciphertexts checked against C references (ModelSim + on-board vectors).

Plot of the first 1200 samples of a power trace captured from the STM32 target — fig.04The first 1200 samples of a ChipWhisperer-NANO power trace from the STM32 target while the firmware runs five division operations.